The present invention is directed to a method of making surface mount semiconductor devices including semiconductor dies with vertically stacked electronic components.
Semiconductor device packaging fulfils basic functions such as providing electric connections and protecting the die against mechanical and environmental stresses. Continuing progress in reduction of the size of the semiconductor dies allows for reducing package size. However, the increased functionality and complexity of the circuits integrated in the dies requires increased external connections, which increases the complexity of reducing the package size.
Semiconductor dies typically are encapsulated for surface mounting. Such surface mount devices often include more than one embedded or encapsulated die. The electrical contacts for connection with external circuits are exposed at the active face of the package and connected internally with electrical contact pads on the semiconductor die. The contacts of the exposed device may be a ball grid array (BGA) or a land grid array (LGA), for example. Various techniques are available for connecting the exposed electrical contacts of the package with the internal contacts of the embedded semiconductor die.
Minimum values are specified for the size of the individual exposed electrical contact surfaces at the active face of the device and for the spacing between adjacent electrical contact surfaces. Such specifications necessitate a compromise between the overall size of the active face of the device and the number of individual electrical contact surfaces.
In a technique known as redistributed chip packaging (RCP), a redistribution layer provides interconnections between the internal contacts on the semiconductor die and the exposed device contacts at the active face of the device. In one technique of assembling embedded RCP devices, singulated dies are placed temporarily with their active faces on a substrate. The dies are encapsulated with a molding compound and then released from the substrate, thereby forming a panel of encapsulated dies. The panel is then processed with wafer processing techniques to build up a redistribution layer which ‘fans out’ the internal contacts of the die to the exposed contacts of the device. The redistribution layer covers an area greater than the area of the active face of the die. The redistribution layer may be built up by depositing successive layers of insulating material with electrical interconnectors in one or more layers, which may have vias providing connections between layers, separated by the insulating layers from each other and from unintended connection with conductive surfaces of the die. The interconnectors are typically deposited by electroplating, and patterned using batch process lithography. Connection with signal input/output and power and ground pads on the active faces of the dies may be made during electro-deposition of the interconnectors and vias. The devices are singulated after completion of the redistribution layer.
A surface mount device including one or more dies with one or more vertically stacked electronic components offers greater circuit complexity with the same or reduced area of the active face. Such a vertically stacked surface mount device may use different technologies such as 3D packaging, system in package (SIP), and package on package (POP), for example. The vertically stacked component may be a processor or a memory component, for example.
Typically, the exposed electrical contact elements of the device are connected with the vertically stacked components through a set of vertical vias. The provision of such vias poses manufacturing issues of reliability, productivity and cost, and is preferably performed without necessitating specific equipment or additional types of manufacturing processes. It would be advantageous to be able to form high quality and reliable vias.